74LS112 J-K Flip-Flop Negative Edge - (AD7198)

Description:

This device contains two independent negative-edge-triggered J-K Flip-Flops with complementary outputs. The J and K data are processed by the flip-flop on the falling edge of the clock pulse. The clock trigger occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs can be changed while the clock is high or low without affecting the outputs, provided that setup and hold times have not been violated. A low logic level on the 'preset' or 'clear' inputs will set or reset the outputs, regardless of the logic levels on the other inputs.

Datasheet