74LS73 Negative JK Flip-Flop - (AD4041)

 

The 74LS73A offers individual J, K, clear and clock inputs. These dual flip-flops are designed so that when the clock goes LOW, the inputs are enabled and data will be accepted. The logic level of the J and K inputs can be allowed to change when the clock pulse is high and the flip-flop will perform according to the truth table, provided that minimum setup times are observed.

Input data is transferred to the outputs on the negative edge of the clock pulses.

- VCC: 4.75-5.25

- Temperature range: 0-70

- High output current: -0.4 mA

- Low output current: 8 mA