74LS194 4-Bit Bidirectional Universal Shift Register - (AD16691)

Description:

This bidirectional shift register is designed to incorporate virtually all the features a systems designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load, Shift right (in the direction QA toward QD), Shift left (in the direction QD toward QA), Inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. Serial data for this mode are entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data are shifted left synchronously and new data are entered at the shift-left serial input. The flip-flop tranditional is inhibited when both mode control inputs are LOW.

Datasheet